Manufacturers of electrical devices such as computers continue to strive to make these devices more efficient. One way to make these devices more efficient is to lower the operating voltage of the device. Hence, many of these devices utilize low voltage processors. Many low voltage processors can operate with a supply voltage of less than one volt. Such low voltage operation allows a device such as a computer to save significant power and run on battery power for extended periods of time. Furthermore, with the advent of multi-core processors, power conservation has become more important for devices such as laptop computers.
New manufacturing technologies such as technologies that can manufacture integrated circuit components that are smaller than 65-nm have created many additional technological challenges for designers of low voltage systems. One such challenge is related to higher intrinsic device variations associated with sub 65-nm manufacturing technology, such as variations in device leakage (Le) and threshold voltages (Vt). Sensitivity of circuit parameters such as device switching at such low voltages due to manufacturing defects is another challenge for designers.
Generally, the minimum operating voltage (Vcc min) of a processor is limited by a minimum voltage that is required by memory systems in order to read from and write to memory cells. It can be appreciated that the amount of high performance data storage (i.e. memory cells) being incorporated with processors is ever increasing. Low voltage sub 65-nm processors that have low voltage, high performance memory typically have a significant yield loss during the testing and burn in procedure. These lower yields have made manufacturers of processors reconsider if lower voltages are economically feasible and what voltage levels are economically practical. Hence, there has been a trend to design and operate current processors at higher voltages than previous processors in an effort to provide an improved cost/performance trade off because of high performance memory problems. It can be appreciated that manufacturers are investing in alternate circuit topologies to the conventional memory structures that can operate at lower voltages and can be manufactured with higher yields.
While reducing the voltage potential of a power supply powering internal IC devices can be beneficial to IC device reliability and power consumption, at the circuit board or system level, the IC still may be coupled to components operating with higher power supply voltages. In that case, the IC may operate with two or more power supplies. Each power supply can provide a different voltage potential to the IC. Typically, one or more low voltage power supplies can be provided to power CMOS devices that drive internal circuits of the IC. One or more high voltage power supplies can be provided to power CMOS devices that receive signals from and/or send signals to, circuits external to the IC. For example, an IC can be provided with a 1.3V power supply for internal circuits and a 3.3V power supply for devices coupled to circuits external to the IC.
Circuits powered by power supplies with differing voltage potentials can output signals with different voltage ranges. For example, one digital circuit powered by a 1.8V power supply can output a signal that varies between 0-1.8V, while another digital circuit powered by a 3.3V power supply may output a signal that varies between 0-3.3V. The difference in signal levels between the two digital circuits can create problems at any interface between the two digital circuits.
For example, consider an interface where a CMOS inverter provides a maximum input voltage of 1.8V to a CMOS inverter operating at 3.3V. The 1.8V input, typically cannot disable a pull-up P-type field effect transistor (pFET) device within the CMOS inverter as −1.5V of gate terminal to source terminal voltage, i.e., 1.8V-3.3V, is being applied to the pFET device. A voltage of −1.5V, however, is sufficient to enable the pFET device. With 1.8V applied to the input of the 3.3V CMOS inverter, both the pull-up pFET device and a pull-down nFET device of the 3.3V CMOS inverter can be enabled simultaneously. In that case, the 3.3V CMOS inverter has a closed current path from the 3.3V power supply to ground when receiving a static input high of 1.8V. As such, the 3.3V CMOS inverter unnecessarily consumes power when in a static state.
In low power central processing units (CPUs), one way to reduce power is to reduce the supply voltage. In order to operate at low voltages, most low voltage memory arrays use an 8T cell, which provides read stability immunity.
However, as supply voltage is decreased, the decrease in performance is not linear. It becomes exponential as the supply is reduced nearer the Vt of the highest-Vt devices, which are typically found in memory arrays for leakage control reasons. In an 8T cell, the write speed limits frequency at low voltage and the various circuits and proposed embodiments disclosed herein solves and addresses many of these issues.